Tessera vs. 南科案 ITC初判

Tessera於2007.12.向美國德州地方法院控告包括南科及其他動態隨機存取記憶體 (DRAM)製造廠及銷售業者侵犯其DRAM封裝的US5,663,106 、US6,133,627及US5,679,977號專利，同時要求ITC進行調查。
本案同時被告的有：力晶、茂德、宏碁、Centon Electronics, Inc.、爾必達 (Elpida；6665-JP)、金士頓 (Kingston)、Ramaxel Technology Ltd.、SMART Modular Technologies、勤茂資通等。
ITC在2009.8.28.初步宣判，Tessera 所提專利權雖然有效，但未受到被告侵犯，預計在2009.12.29.會做出最終判決。

US5,663,106
Title:Method of encapsulating die and chip carrier
Filing Date:1994.5.19.
Issue Date:1997.9.2.
Abstract:
A method of packaging a semiconductor chip assembly includes the encapsulation of the same after establishing an encapsulation area and providing a physical barrier for protecting the terminals of a chip carrier. An alternative or supplement to providing a physical barrier is to provide a preform of an encapsulation material which includes a predetermined volume of such material so that only the encapsulation area is filled. For a semiconductor chip assembly which does not yet have an elastomeric layer, a method of simultaneously forming such an elastomeric layer and encapsulating a semiconductor chip assembly is also provided.

US5,679,977
Title:Semiconductor chip assemblies, methods of making same and components for same
Filing Date:1993.4.28.
Issue Date:1997.10.21.
Abstract:
Semiconductor chip assemblies incorporating flexible, sheet-like elements having terminals thereon overlying the front or rear face of the chip to provide a compact unit. The terminals on the sheet-like element are movable with respect to the chip, so as to compensate for thermal expansion. A resilient element such as a compliant layer interposed between the chip and terminals permits independent movement of the individual terminals toward the chip driving engagement with a test probe assembly so as to permit reliable engagement despite tolerances.

US6,133,627
Title:Semiconductor chip package with center contacts
Filing Date:1997.12.3.
Issue Date:2000.10.17.
Abstract:
A semiconductor chip having contacts on the central region of its top surface is provided with a dielectric element overlying the central portion of the top surface. The dielectric element has a first surface facing toward the chip and a second surface facing away from the chip, a hole encompassing the central contacts and an edge bounding the hole. Central contact leads extend from the central contacts on the chip to central terminals on the dielectric element. The terminals on the dielectric element may be connected to a substrate using techniques commonly employed in surface mounting of electrical devices, such as solder bonding. The leads, and preferably the dielectric element, are flexible so that the terminals are moveable with respect to the contacts on the chip, to compensate for differential thermal expansion of the chip and substrate. The dielectric element may be provided with a compliant layer disposed between the terminals and the chip. The entire assembly is compact.