BIAX發起軟體訴訟

美國科羅拉多州的電腦製造商BIAX於2010.12.13.向科羅拉多州聯邦地方法院控訴Motorola、HP、Cisco以及日商Canon、Brother、Ricoh之美國分公司與其日本母公司侵害其US5,517,628與US6,253,313專利。

US5,517,628
Title : Computer with instructions that use an address field to select among multiple condition code registers
Filing Date : 1994.6.6.
Issue Date : 1996.5.14.
Abstract :
The invention features a computer with a condition code register file (the condition code register file is distinct from the computer\'s general purpose register file). The condition code register file has a plurality of addressable condition code registers. The computer executes condition-setting instructions that each produce a condition code value for storage in one of the condition code registers, and conditional branch instructions that branch to a target based on analysis of a condition code value from one of the condition code registers. The condition code registers are directly addressable by condition code address fields of the instructions. The invention finds primary expression in one of two embodiments (or in both simultaneously): either (a) at least some of the condition-setting instructions contain a direct address field that selects one, from among the plurality of the condition code registers into which the condition code value is to be stored, or (b) at least some of the conditional branch instructions contain a direct address field that selects one, from among the plurality of the condition code registers from which a condition code value is to be selected for analysis.

US6,253,313
Title : Parallel processor system for processing natural concurrencies and method therefor
Filing Date : 1995.6.7.
Issue Date : 2001.6.26.
Abstract :
A computer processing system containing a plurality of identical processor elements each of which does not retain execution state information from prior operations. The plurality of identical processor elements operate on a statically compiled program which, based upon detected natural concurrencies in the basic blocks of the programs, provide logical processor numbers and an instruction firing time to each instruction in each basic block. Each processor element is capable of executing instructions on a per instruction basis such that dependent instructions can execute on the same or different processor elements. A given processor element is capable of executing an instruction from one context followed by an instruction from another context through use of shared storage resources.